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     . attachment:orange.png make realtime simlink model      . attachment:green.png make realtime simlink model

September CDS plan

Major Missions

  • {*} Complete damping of the vertex suspensions

  • {*} Preparation for Green locking

  • {*} Simulated plants

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category

description

Links

plans and overviews

CDS home page

[:Upgrade_09/CDS]

CDS plan for August

[:Upgrade_09/CDS/August_CDS_test]

Simulated Plant

[:Simulated_Plant]

Lists

Current Hardware Lists

[:Upgrade_09/CDS/current_hardware]

Channel Assignments for C1SUS

[:Upgrade_09/CDS/Suspension_wiring_to_channels]

Technical Notes

Notes about CDS realtime code

[:Notes_on_getting_the_CDS_Realtime_Code_Generator_working]

Notes for Green Locking interface to realtime code

[:Notes_for_Green_locking_interface_to_RCG]

Notes for Simulated Plant

[:Notes_for_the_RCG_40m_simulated_plant]

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PLANS

TO DO LIST

  • attachment:green.png complete

    attachment:orange.png intermediate state

    attachment:red.png incomplete

    attachment:black.png gave up

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  • A. Complete suspension damping keeping in mind Version B coils. (1-2 days?)

    • ADC break out boards

      • attachment:orange.png design an adapter box for the breakout boards
      • attachment:red.png make the box and install it

    • Binary Output working on c1sus (Alex/Joe) 1-2 days

      • attachment:orange.png test all the BO channels and their assignments
      • attachment:green.png Switching over cabling from the current XY220's to the new system

    • damping test with the BOs

      • attachment:green.png damping all the vertex suspensions with the new CDS
      • attachment:green.png check if the binary outputs are working
      • attachment:orange.png make the daq daemon work

    • refinement of the control model

      • attachment:green.png renewal of realtime control model
      • attachment:orange.png renewal of medm screens for the vertex suspensions

    • misc.

      • attachment:green.png fix  feCodeGen.pl  script

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  • B. Preparation for Green Locking

    • Get RFM working (3-4 days)

      • attachment:green.png make a new IPC parser
      • attachment:green.png string the RFM optical fiber connecting C1SUS and C1ISCEX
      • attachment:green.png install PCI-5565 driver if it's necessary
      • attachment:orange.png test the RFM card by running the diagnostic script on the individually
      • attachment:orange.png test the RFM with the epics

    • Get both end stations working

      • attachment:red.png Check we have correct number of cables
      • attachment:green.png Check if both end stations are correctly running

    • Get IOO front end machine working

      • attachment:green.png Move the computer into 1X2 rack
      • attachment:green.png remove Marconi(?) and put a new IO chassis on 1X2 rack
      • attachment:green.png check timing/ADC/DAC on the IO chassis. And make it works (5 days)

    • Fix non-working IO chassis

      • attachment:green.png Check on fiber with Rolf for LSC
      • attachment:green.png timing/ADC/DAC check

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  • C. Simulated Plant

    • Simulated Green Locking

      • attachment:green.png conceptual design
      • attachment:green.png make realtime simlink model
      • attachment:orange.png compile and install the model

    • LSC simulated plant

      • attachment:green.png conceptual design
      • attachment:green.png make realtime simlink model
      • attachment:orange.png compile and install the model

    • Gentoo patch (not high priority)

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PSL Racks Setup

attachment:1X1_1X2_racks.png

New rack setup in pdf form attachment:1X1_1X2_racks.pdf

WISH LIST

(not urgent things, but somethings we want to implement at some points)

  • channel wiki

  • wiki hyperlink on a medm screen

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TIME LINE SCHEDULE

  • Put time line schedule here.

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DETAILED CONSIDERATIONs

Cable Requirements

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Notes about Binary Outputs

  • To obtain a voltage signal, a pull-up resister and a DC voltage are needed at the receiver stage because the signal is generated with a transistor.
  • An easy way to check this BO system is putting an LED on the receiver stage as described in the figure below. In this case if the signal is ON the LED lights up and vice versa.

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    normal operation

    test configuration

    BO_final.png

    BO_test.png

  • A datasheet for the BO card is here attachment:contec32BO.pdf

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Reflective Memory Network

  • What is the temporary configuration ?
  • What is the final configuration ?

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Simulated Plant for Green locking

Conceptual Design

  • green_sm.png

    • The control signals from the realtime control model (RCM) "GRN" goes to the suspension RCM "SUS, SCX and SCY"
  • Then the signal of coil actuation will drive a simulated suspension called "SUP and SPX/Y" instead of the real suspensions.
  • In the simulated plant each model mimics the response of the real interferometer, suspensions, PDs and so on.
  • After the signal goes through the simulated plant, the signal eventually come back to the RCMs as fake PD readouts.

  • green_simlated_plant.png

Model construction

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Gain Mismatch

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CDS/September_CDS_plan (last edited 2012-01-03 23:02:37 by localhost)