September CDS plan
Major Missions
Complete damping of the vertex suspensions
Preparation for Green locking
Simulated plants
Useful Links
category |
description |
Links |
plans and overviews |
CDS home page |
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CDS plan for August |
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Simulated Plant |
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Lists |
Current Hardware Lists |
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Channel Assignments for C1SUS |
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Technical Notes |
Notes about CDS realtime code |
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Notes for Green Locking interface to realtime code |
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Notes for Simulated Plant |
PLANS
TO DO LIST
complete
intermediate state
incomplete
gave up
A. Complete suspension damping keeping in mind Version B coils. (1-2 days?)
ADC break out boards
design an adapter box for the breakout boards
make the box and install it
Binary Output working on c1sus (Alex/Joe) 1-2 days
rearrange the channel assignments
test all the BO channels and their assignments
Switching over cabling from the current XY220's to the new system
damping test with the BOs
damping all the vertex suspensions with the new CDS
check if the binary outputs are working
make the daq daemon work
refinement of the control model
renewal of realtime control model
renewal of medm screens for the vertex suspensions
separate optics into some realtime models instead of one model in order to avoid run time issues
misc.
fix feCodeGen.pl script
B. Preparation for Green Locking
Get RFM working (3-4 days)
make a new IPC parser
string the RFM optical fiber connecting C1SUS and C1ISCEX
switching the RFM old network to that of the new one by using the RFM bypath
install PCI-5565 driver if it's necessary
test the RFM card by running the diagnostic script
test the RFM with the epics
Get both end stations working
Check we have correct number of cables
Check if both end stations are correctly running
Get IOO front end machine working
Move the computer into 1X2 rack
remove Marconi(?) and put a new IO chassis on 1X2 rack
check timing/ADC/DAC on the IO chassis. And make it works (5 days)
Fix non-working IO chassis
Check on fiber with Rolf for LSC
timing/ADC/DAC check
C. Simulated Plant
Simulated Green Locking
conceptual design
make realtime simlink model
compile and install the model
LSC simulated plant
conceptual design
make realtime simlink model
compile and install the model
SUS simulated plant
renew the model with the new CDS parts
compile and install the model
D. Frame builder
rebuild frame builder
rebuild the frame builder by Gentoo OS
get dataviewer working
install a heavy duty DAQ router
diskless boot
diskless boot seetings on the frame builder
run the front end machines with Gentoo realtime core
run a realtime code on a new realtime Gentoo
PSL Racks Setup
New rack setup in pdf form 1X1_1X2_racks.pdf
WISH LIST
(not urgent things, but somethings we want to implement at some points)
channel wiki
wiki hyperlink on a medm screen
TIME LINE SCHEDULE
- Put time line schedule here.
DETAILED CONSIDERATIONs
Cable Requirements
- Do we have sufficient number of the cables ?
- Let's doublecheck it.
Notes about Binary Outputs
- To obtain a voltage signal, a pull-up resister and a DC voltage are needed at the receiver stage because the signal is generated with a transistor.
- An easy way to check this BO system is putting an LED on the receiver stage as described in the figure below. In this case if the signal is ON the LED lights up and vice versa.
A datasheet for the BO card is here contec32BO.pdf
Reflective Memory Network
- What is the temporary configuration ?
- What is the final configuration ?
Simulated Plant for Green locking
Conceptual Design
Model construction
Gain Mismatch




