September CDS plan

Major Missions

• Complete damping of the vertex suspensions

• Preparation for Green locking

• Simulated plants

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Useful Links

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PLANS

TO DO LIST

• attachment:green.png complete

  attachment:orange.png intermediate state

  attachment:red.png incomplete

  attachment:black.png gave up

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• A. Complete suspension damping keeping in mind Version B coils. (1-2 days?)

  • ADC break out boards

    • attachment:red.png design an adapter box for the breakout boards
    • attachment:red.png make the box and install it

  • Binary Output working on c1sus (Alex/Joe) 1-2 days

    • attachment:orange.png test all the BO channels and their assignments
    • attachment:red.png Switching over cabling from the current XY220's to the new system

  • damping test with the BOs

    • attachment:green.png damping all the vertex suspensions with the new CDS
    • attachment:red.png check if the binary outputs are working

  • refinement of the control model

    • attachment:red.png renewal of realtime control model
    • attachment:red.png renewal of medm screens for the vertex suspensions

  • misc.

    • attachment:red.png fix  feCodeGen.pl  script

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• B. Preparation for Green Locking

  • Get RFM working (3-4 days)

    • attachment:red.png make a new IPC parser
    • attachment:green.png string the RFM optical fiber connecting C1SUS and C1ISCEX
    • attachment:orange.png install PCI-5565 driver on c1sus
    • attachment:red.png install PCI-5565 driver on c1iscex
    • attachment:red.png test the RFM card by running the diagnostic script on the individually
    • attachment:red.png test the RFM with the epics

  • Get both end stations working

    • attachment:red.png Check we have correct number of cables (again tomorrow).
    • attachment:red.png Check if both end stations are correctly running

  • Get IOO front end machine working

    • attachment:red.png Move the computer into 1X2 rack
    • attachment:red.png remove Marconi(?) and put a new IO chassis on 1X2 rack
    • attachment:red.png check timing/ADC/DAC on the IO chassis. And make it works (5 days)

  • Fix non-working IO chassis

    • attachment:red.png Check on fiber with Rolf for LSC
    • attachment:red.png timing/ADC/DAC check

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• C. Simulated Plant

  • Simulated Green Locking

    • attachment:red.png conceptual design
    • attachment:red.png make realtime simlink model
    • attachment:red.png compile and install the model

  • LSC simulated plant

    • attachment:green.png conceptual design
    • attachment:green.png make realtime simlink model
    • attachment:orange.png compile and install the model

  • Gentoo patch (not high priority)

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WISH LIST

(not urgent things, but somethings we want to implement at some points)

• channel wiki

• wiki hyperlink on a medm screen

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TIME LINE SCHEDULE

• Put time line schedule here.

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DETAILED CONSIDERATIONs

Cable Requirements

• Do we have sufficient number of the cables ?
• Let's doublecheck it.

• Current Hardwares Lists

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Notes about Binary Outputs

• To obtain a voltage signal, a pull-up resister and a DC voltage are needed at the receiver stage because the signal is generated with a transistor.
• An easy way to check this BO system is putting a LED on the receiver stage as described in the figure below. In this case if the signal is ON the LED lights up and vice versa.

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  normal operation	test configuration

• A datasheet for the BO card is here attachment:contec32BO.pdf

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Reflective Memory Network

• What is the temporary configuration ?
• What is the final configuration ?

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Simulated Plant for Green locking

• Concept
• Model construction

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