-  ⇤ ← Revision 3 as of 2010-09-07 18:37:37 → 
  Size: 1012
  Editor: KiwamuIzumi
  Comment:
+   ← Revision 54 as of 2010-09-22 18:24:08 → ⇥
  Size: 5206
  Editor: JoeBetzwieser
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 3:
-= TO DO LIST =
|| attachment:green.png '''complete'''|| attachment:orange.png '''intermediate state ''' || attachment:red.png '''incomplete''' || attachment:black.png gave up||
+== Major Missions ==
-Line 6:
+Line 5:
- . attachment:orange.png Binary Output working (Alex/Joe) 1-2 days
+ . {*} Complete damping of the vertex suspensions
 . {*} Preparation for Green locking
 . {*} Simulated plants
-Line 8:
+Line 9:
-Complete suspension damping keeping in mind Version B coils. (1-2 days?)
  
Get RFM working! (We have new parts and need new IPC parser) (3-4 days)
+[[BR]]
-Line 12:
+Line 11:
-Get both end stations working.  Check we have correct number of cables (againi tomorrow).
+== Useful Links ==
|| ''''' category'''''|| ''''' description ''''' || ''''' Links '''''||
||<|3> plans and overviews|| ''' CDS home page ''' || [:Upgrade_09/CDS] ||
|| ''' CDS plan for August ''' || [:Upgrade_09/CDS/August_CDS_test] ||
|| ''' Simulated Plant''' ||[:Simulated_Plant] ||
||<|2> Lists || ''' Current Hardware Lists ''' || [:Upgrade_09/CDS/current_hardware] ||
|| ''' Channel Assignments for C1SUS ''' || [:Upgrade_09/CDS/Suspension_wiring_to_channels] ||
||<|3> Technical Notes || ''' Notes about CDS realtime code ''' || [:Notes_on_getting_the_CDS_Realtime_Code_Generator_working] ||
|| ''' Notes for Green Locking interface to realtime code ''' || [:Notes_for_Green_locking_interface_to_RCG] ||
|| ''' Notes for Simulated Plant ''' ||[:Notes_for_the_RCG_40m_simulated_plant] ||
-Line 14:
+Line 22:
-Get IOO working. (Get thing computer into 1X1 or 1X2 rack, get IO chassis into 1X1 or 1X2 working. (5 days)
+[[BR]]
----------------
= PLANS =
== TO DO LIST ==
 || attachment:green.png '''complete'''|| attachment:orange.png '''intermediate state ''' || attachment:red.png '''incomplete''' || attachment:black.png gave up||

 [[BR]]
 . ''' A. Complete suspension damping keeping in mind Version B coils. (1-2 days?) '''
   . ''' ADC break out boards '''
     . attachment:red.png design an adapter box for the breakout boards
     . attachment:red.png make the box and install it
   . ''' Binary Output working on c1sus (Alex/Joe) 1-2 days '''
     . attachment:orange.png test all the BO channels and their assignments
     . attachment:red.png Switching over cabling from the current XY220's to the new system
   . ''' damping test with the BOs'''  
     . attachment:green.png  damping all the vertex suspensions with the new CDS
     . attachment:red.png check if the binary outputs are working
     . attachment:red.png make the daq daemon work
   . ''' refinement of the control model '''
     . attachment:orange.png renewal of realtime control model
     . attachment:red.png renewal of medm screens for the vertex suspensions
   . ''' misc. '''
     . attachment:orange.png fix {{{ feCodeGen.pl }}} script
[[BR]]
 . ''' B. Preparation for Green Locking '''
   . ''' Get RFM working (3-4 days) '''
     . attachment:green.png make a new IPC parser 
     . attachment:green.png string the RFM optical fiber connecting C1SUS and C1ISCEX
     . attachment:orange.png install PCI-5565 driver on c1sus
     . attachment:red.png install PCI-5565 driver on c1iscex
     . attachment:red.png test the RFM card by running the diagnostic script on the individually
     . attachment:red.png test the RFM with the epics
-Line 16:
+Line 57:
-Simulated Green Locking.
+   .  ''' Get both end stations working '''
     . attachment:red.png Check we have correct number of cables (again tomorrow).
     . attachment:red.png Check if both end stations are correctly running

   . ''' Get IOO front end machine working '''
     . attachment:red.png Move the computer into 1X2 rack
     . attachment:red.png remove Marconi(?) and put a new IO chassis on 1X2 rack
     . attachment:red.png check timing/ADC/DAC on the IO chassis. And make it works (5 days)
   . ''' Fix non-working IO chassis '''
     . attachment:red.png  Check on fiber with Rolf for LSC
     . attachment:red.png timing/ADC/DAC check

 [[BR]]

 . ''' C. Simulated Plant '''
   . ''' Simulated Green Locking '''
     . attachment:red.png conceptual design
     . attachment:red.png make realtime simlink model
     . attachment:red.png compile and install the model
-Line 18:
+Line 77:
-Either Green locking or simulated plant LSC (or in parallel).
+   . ''' LSC simulated plant '''
     . attachment:green.png conceptual design 
     . attachment:green.png make realtime simlink model
     . attachment:orange.png compile and install the model
   . ''' Gentoo patch ''' (not high priority)
-Line 20:
+Line 84:
-Fix non-working IO chassis (today).  Check on fiber with Rolf for LSC.
+[[BR]]
[[BR]]

== PSL Racks Setup ==

attachment:1X1_1X2_racks.png New rack setup

== WISH LIST ==
(not urgent things, but somethings we want to implement at some points)

 . ''' channel wiki '''
 . ''' wiki hyperlink on a medm screen '''


[[BR]]
[[BR]]

== TIME LINE SCHEDULE ==

 . Put time line schedule here.
[[BR]]
[[BR]]

-----------
= DETAILED CONSIDERATIONs =
== Cable Requirements ==

 . Do we have sufficient number of the cables ?
 . Let's doublecheck it.

 . {i} [[Upgrade_09/CDS/current_hardware|Current Hardwares Lists]]

[[BR]]
[[BR]]

== Notes about Binary Outputs ==

 . To obtain a voltage signal, a pull-up resister and a DC voltage are needed at the receiver stage because the signal is generated with a transistor.
 . An easy way to check this BO system is putting an LED on the receiver stage as described in the figure below. In this case if the signal is ON the LED lights up and vice versa.

 [[BR]]

 || ''' normal operation ''' || ''' test configuration ''' ||
 || <<ImageLink(BO_final.png, void, height=260)>> || <<ImageLink(BO_test.png, void, height=260)>> ||


 . A datasheet for the BO card is here attachment:contec32BO.pdf

[[BR]]
[[BR]]

== Reflective Memory Network ==

 . What is the temporary configuration ?

 . What is the final configuration ?

[[BR]]
[[BR]]

== Simulated Plant for Green locking ==

 . Concept
-Line 22:
+Line 148:
-Simulated Green Locking.
+ . Model construction
-Line 24:
+Line 150:
-Either Green locking or simulated plant LSC (or in parallel).
+[[BR]]
[[BR]]
-Line 26:
+Line 153:
-Gentoo patch (not high priority - unless they stop making backwards compatibility - do it when we have time).
+== Gain Mismatch ==
[[BR]]
[[BR]]

category	description	Links
plans and overviews	CDS home page	[:Upgrade_09/CDS]
	CDS plan for August	[:Upgrade_09/CDS/August_CDS_test]
	Simulated Plant	[:Simulated_Plant]
Lists	Current Hardware Lists	[:Upgrade_09/CDS/current_hardware]
Lists	Channel Assignments for C1SUS	[:Upgrade_09/CDS/Suspension_wiring_to_channels]
Technical Notes	Notes about CDS realtime code	[:Notes_on_getting_the_CDS_Realtime_Code_Generator_working]
	Notes for Green Locking interface to realtime code	[:Notes_for_Green_locking_interface_to_RCG]
	Notes for Simulated Plant	[:Notes_for_the_RCG_40m_simulated_plant]

normal operation	test configuration

September CDS plan

Major Missions

Useful Links

PLANS

TO DO LIST

PSL Racks Setup

WISH LIST

TIME LINE SCHEDULE

DETAILED CONSIDERATIONs

Cable Requirements

Notes about Binary Outputs

Reflective Memory Network

Simulated Plant for Green locking

Gain Mismatch