Differences between revisions 3 and 33 (spanning 30 versions)
⇤ ← Revision 3 as of 2010-09-07 18:37:37 →
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Editor: KiwamuIzumi
Comment:
← Revision 33 as of 2010-09-08 04:31:19 → ⇥
Size: 3873
Editor: KiwamuIzumi
Comment:
Deletions are marked like this. Additions are marked like this.
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= TO DO LIST =
|| attachment:green.png '''complete'''|| attachment:orange.png '''intermediate state ''' || attachment:red.png '''incomplete''' || attachment:black.png gave up||		 == Major Missions ==
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 . attachment:orange.png Binary Output working (Alex/Joe) 1-2 days  . {*} Complete damping of the vertex suspensions
 . {*} Preparation for Green locking
 . {*} Simulated plants
Line 8: Line 9:
Complete suspension damping keeping in mind Version B coils. (1-2 days?)
  
Get RFM working! (We have new parts and need new IPC parser) (3-4 days)
Line 12: Line 10:
Get both end stations working. Check we have correct number of cables (againi tomorrow). [[BR]]
[[BR]]
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Get IOO working. (Get thing computer into 1X1 or 1X2 rack, get IO chassis into 1X1 or 1X2 working. (5 days) == Links ==
 . {i} [[Upgrade_09/CDS/current_hardware|Current Hardwares Lists]]

----------------
= PLANS =
== TO DO LIST ==
 || attachment:green.png '''complete'''|| attachment:orange.png '''intermediate state ''' || attachment:red.png '''incomplete''' || attachment:black.png gave up||

 [[BR]]
 . ''' A. Complete suspension damping keeping in mind Version B coils. (1-2 days?) '''
   . ''' ADC break out boards '''
     . attachment:red.png design an adapter box for the breakout boards
     . attachment:red.png make the box and install it
   . ''' Binary Output working on c1sus (Alex/Joe) 1-2 days '''
     . attachment:orange.png test all the BO channels and their assignments
     . attachment:red.png Switching over cabling from the current XY220's to the new system
   . ''' damping test with the BOs'''
     . attachment:green.png damping all the vertex suspensions with the new CDS
     . attachment:red.png check if the binary outputs are working
   . ''' refinement of the control model '''
     . attachment:red.png renewal of realtime control model
     . attachment:red.png renewal of medm screens for the vertex suspensions
   . ''' misc. '''
     . attachment:red.png fix {{{ feCodeGen.pl }}} script
[[BR]]
 . ''' B. Preparation for Green Locking '''
   . ''' Get RFM working (3-4 days) '''
     . attachment:red.png make a new IPC parser
     . attachment:green.png string the RFM optical fiber connecting C1SUS and C1ISCEX
     . attachment:orange.png install PCI-5565 driver on c1sus
     . attachment:red.png install PCI-5565 driver on c1iscex
     . attachment:red.png test the RFM card by running the diagnostic script on the individually
     . attachment:red.png test the RFM with the epics
Line 16: Line 48:
Simulated Green Locking.    . ''' Get both end stations working '''
     . attachment:red.png Check we have correct number of cables (again tomorrow).
     . attachment:red.png Check if both end stations are correctly running

   . ''' Get IOO front end machine working '''
     . attachment:red.png Move the computer into 1X2 rack
     . attachment:red.png remove Marconi(?) and put a new IO chassis on 1X2 rack
     . attachment:red.png check timing/ADC/DAC on the IO chassis. And make it works (5 days)
   . ''' Fix non-working IO chassis '''
     . attachment:red.png Check on fiber with Rolf for LSC
     . attachment:red.png timing/ADC/DAC check

 [[BR]]

 . ''' C. Simulated Plant '''
   . ''' Simulated Green Locking '''
     . attachment:red.png conceptual design
     . attachment:red.png make realtime simlink model
     . attachment:red.png compile and install the model
Line 18: Line 68:
Either Green locking or simulated plant LSC (or in parallel).    . ''' LSC simulated plant '''
     . attachment:green.png conceptual design
     . attachment:green.png make realtime simlink model
     . attachment:orange.png compile and install the model
   . ''' Gentoo patch ''' (not high priority)
Line 20: Line 75:
Fix non-working IO chassis (today). Check on fiber with Rolf for LSC. [[BR]]
[[BR]]

== WISH LIST ==
(not urgent things, but somethings we want to implement at some points)

 . ''' channel wiki '''
 . ''' wiki hyperlink on a medm screen '''




== TIME LINE SCHEDULE ==

 . Put time line schedule here.
[[BR]]
[[BR]]

-----------
= DETAILED CONSIDERATIONs =
== Cable Requirements ==

 . Do we have sufficient number of the cables ?
 . Let's doublecheck it.

[[BR]]
[[BR]]

== Notes about Binary Outputs ==
=== Principle of the signal transfer ===
 . A signal generated at Contec BO 32 boards
 . attachment:BO_final.png
=== A technique to check the BO signal ===

 . attachment:BO_test.png

[attachment:]

[[BR]]
[[BR]]

== Reflective Memory Network ==

 . What is the temporary configuration ?

 . What is the final configuration ?

[[BR]]
[[BR]]

== Simulated Plant for Green locking ==

 . Concept
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Simulated Green Locking.  . Model construction
Line 24: Line 131:
Either Green locking or simulated plant LSC (or in parallel).

Gentoo patch (not high priority - unless they stop making backwards compatibility - do it when we have time).
 		 [[BR]]
[[BR]]

September CDS plan

Major Missions

  • {*} Complete damping of the vertex suspensions

  • {*} Preparation for Green locking

  • {*} Simulated plants

BR BR

PLANS

TO DO LIST

  • attachment:green.png complete

    attachment:orange.png intermediate state

    attachment:red.png incomplete

    attachment:black.png gave up

    BR

  • A. Complete suspension damping keeping in mind Version B coils. (1-2 days?)

    • ADC break out boards

      • attachment:red.png design an adapter box for the breakout boards
      • attachment:red.png make the box and install it

    • Binary Output working on c1sus (Alex/Joe) 1-2 days

      • attachment:orange.png test all the BO channels and their assignments
      • attachment:red.png Switching over cabling from the current XY220's to the new system

    • damping test with the BOs

      • attachment:green.png damping all the vertex suspensions with the new CDS
      • attachment:red.png check if the binary outputs are working

    • refinement of the control model

      • attachment:red.png renewal of realtime control model
      • attachment:red.png renewal of medm screens for the vertex suspensions

    • misc.

      • attachment:red.png fix  feCodeGen.pl  script

BR

  • B. Preparation for Green Locking

    • Get RFM working (3-4 days)

      • attachment:red.png make a new IPC parser
      • attachment:green.png string the RFM optical fiber connecting C1SUS and C1ISCEX
      • attachment:orange.png install PCI-5565 driver on c1sus
      • attachment:red.png install PCI-5565 driver on c1iscex
      • attachment:red.png test the RFM card by running the diagnostic script on the individually
      • attachment:red.png test the RFM with the epics

    • Get both end stations working

      • attachment:red.png Check we have correct number of cables (again tomorrow).
      • attachment:red.png Check if both end stations are correctly running

    • Get IOO front end machine working

      • attachment:red.png Move the computer into 1X2 rack
      • attachment:red.png remove Marconi(?) and put a new IO chassis on 1X2 rack
      • attachment:red.png check timing/ADC/DAC on the IO chassis. And make it works (5 days)

    • Fix non-working IO chassis

      • attachment:red.png Check on fiber with Rolf for LSC
      • attachment:red.png timing/ADC/DAC check

    BR

  • C. Simulated Plant

    • Simulated Green Locking

      • attachment:red.png conceptual design
      • attachment:red.png make realtime simlink model
      • attachment:red.png compile and install the model

    • LSC simulated plant

      • attachment:green.png conceptual design
      • attachment:green.png make realtime simlink model
      • attachment:orange.png compile and install the model

    • Gentoo patch (not high priority)

BR BR

WISH LIST

(not urgent things, but somethings we want to implement at some points)

  • channel wiki

  • wiki hyperlink on a medm screen

TIME LINE SCHEDULE

  • Put time line schedule here.

BR BR

DETAILED CONSIDERATIONs

Cable Requirements

  • Do we have sufficient number of the cables ?
  • Let's doublecheck it.

BR BR

Notes about Binary Outputs

Principle of the signal transfer

  • A signal generated at Contec BO 32 boards
  • attachment:BO_final.png

A technique to check the BO signal

  • attachment:BO_test.png

[attachment:]

BR BR

Reflective Memory Network

  • What is the temporary configuration ?
  • What is the final configuration ?

BR BR

Simulated Plant for Green locking

  • Concept
  • Model construction

BR BR

CDS/September_CDS_plan (last edited 2012-01-03 23:02:37 by localhost)