SUS Noise Monitor

Design goals

• No saturations as long as the coil driver input signals are at the 99th percentile or below.
• Provide enough gain (at 20 Hz and above) to boost the DAC noise above ADC noise (by what factor?).
• Is it possible to measure the coil driver noise? Or alternatively, with what SNR should the DAC noise be measured?

Design inputs

• DAC noise model: page 6 of G1401399.

• PUM coil driver transfer function. LISO models are available here.

• The worst-case dewhitening state for the noise monitor is ACQ off, LP on.

• ADC noise level, about 4 uV/rtHz. (Reference: page 6 of T070213)

• Coil driver input spectra, G1801540.

• The aLIGO sensitivity curve, T1500293.

• Quad suspension PUM transfer function: above a few Hz, about 3e-8*(10 Hz/f)⁴ m/N. (Reference: T1100595)

DAC noise

The DAC noise model is given in the design inputs above G1401399. We calculate the output current of the coil driver using the Liso models given above in the design input here. Since the DAC is the lowest when ACQ is off and LP is on, it is the worst case for our design of the noise monitor. Hence, ACQ on, LP off is the state we choose to evaluate our design. Then we calculate how much driving force can be generated from the output current of the coil driver according to the block diagram of the PUM coil driver. Finally, we calculate how much strain is produced out of the DAC noise using the mechanical transfer function at T1100595, given in the design input above and estimated to be about 3e-8*(10 Hz/f)⁴ m/N. The DAC noise is plotted DAC-noise-strain.pdf, compared with the aLIGO strain noise. The "10" in DAC-noise-strain-10 means the noise when LP is ON and ACQ is OFF. The aLIGO-strain-requirement curve is the aLIGO noise curve divided by 10. We want the internal noise of our noise monitor to be lower than the DAC noise.

A marginal observation has been made comparing the DAC noises of different states of the coil driver. A plot comparing the noises under three different states with the aLIGO noise has been made DAC-noise-CDstates-strain.pdf. Similar as above, "00" means both LP and ACQ are turned off; "01" means that LP is OFF and ACQ is ON. We can see that, at 20 Hz, when the acq turns on or lp turns off, DAC noise increases by roughly a factor of 10. If they both happen, DAC noise increases by almost a factor of 100. This comes from the change of the current transfer function with coil driver states. When you turn on the acq, or turn off the lp, you get more current out of the coil driver for the same voltage. Plots of the transfer functions: tf-CDstates.pdf.

Some design thoughts 8/5

• The current design uses a couple passive filters, interleaved by amplifiers. Passband 0.482Hz - 482Hz, gain ~200. Combining with the coil driver transfer function, the signal is amplified about 40 times from the input of the coil driver. Compared with the given input signal, it seems the saturation is mainly caused by low frequency signals below 10Hz.
• Following Rana's idea on Friday: a pair of low/high pass filter + instrument amplifier (where we get the gain), what else do we need?
  • Sharper cutoff (Higher Q)? Perhaps higher order passive filters?
  • Noise? Input impedance?
• If we have a good filter, according to the input spectrum, maybe applying a gain of 500? This allows the 300nV DAC noise to overwhelm the 4uV ADC noise. This also keeps the signal away from saturation, according to the given coil driver input spectrum. Do we have to worry about the strong mode at 500 Hz in both H1 and L1?
• Trying to learn about active filters. Would we consider using them?

Decisions 8/6

• Start from the existing design but
  • spread the gain across the stages to manage risk of saturation
  • Move the low frequency cutoff to 20Hz
• Move on to active filters for better stop band to pass band transition

Progress 8/7

• Used WEBENCH Designer (Free TI filter designing software) and got a Chebyshev high pass filter with 5 stages of Sallen-Key filters. It has a sharp transition below 20Hz, attenuating 15Hz to -15dB; 10Hz to -50dB, as is shown in simulations. I also put a passband gain of 20 on the filters. The design and simulation results are uploaded. webench_esim_5774067_1_1_774987413.pdf

• Plan to layout as such: Instrumental AMP (Gain 10) -> High pass filters (the Chebyshey above) -> high pass filters (Sallen-and-key filters, modification to the existing design)

• Test the noise in LISO
• Build it downstairs in the lab
• If saturates, we might consider moving the instrumental AMP between the stages in the Chebyshey filter.
• We hope the noise is tolerable.

LISO model and noise 8/8

• Design/simulation documentsdesign.zip

• Following yesterday's layout idea of "Instrumental amplifier -> high pass filter (5 stage Chebyshev) -> low pass filter (Sallen Key)", I constructed the LISO model and tested the transfer function and noise.

• Concerned about the risk of saturation, I put the instrumental amplifier between the first and second stage, and thus duplicated the first stage for the positive and negative inputs.
• I changed the Opamps to LT1792, used by the original design. The one chosen by WEBENCH is OPA2227PA.
• I did not know the input impedance, set to 50 Ohm by LISO and warned.
• The high pass filter quality at 20Hz is satisfactory.
• The noise is too much.
• Plan to put the instrumental amplifier back to the beginning and see how much that is going to help the noise. Or maybe the input impedance can make a difference here?

Noise and Saturation test 8/12

• Saturation: it seems the circuit might not saturate. Output RMS: 0.937V/sqrt(Hz). saturation-test.jpgoutput.jpg

• Noise: we need to reduce the noise. noise.pdf

Noise comparisons 8/14

noise-strain.pdf

• Created a git repository.

• Compared the aligo noise, noise component requirement (aligo/10), the DAC noise, and the noise of the first design.
• It seems true, as Rana mentioned, that we do not need to care about the DAC noise above 100Hz.
• The DAC noise is below the noise requirement.
• Our version 1 design has too much noise, not good enough to detect the DAC noise.