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| = Dither-based Alignment Sensing and Stabilization = | |
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| ---- * Design and ASC scheme after we design one for AdvLIGO * Implement and test the new InGaAs, in-vac, high power, FTC WFS. The 40m WFS need not be . in-vac, but they should be packaged as such. * Measure spring stuff |
<<TableOfContents()>> = Overview = . The idea is to dither (in pitch and yaw) all of the interferometer optics. We then read out the power (arm powers, PRC power, etc.) and demodulate at the dither frequencies. We can then feedback to control the full interferometer alignment. The concept is the same as what we use to do the initial alignment of the interferometer. It was previously tried by Valera and Bram, but never worked for some reason... * [attachment:ass.png Conceptual Diagram] * See also the old [[Alignment Sensing and Control]]. |
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| ---- . [[Simulink Model of 40m Optical Springs]] |
= Control Topologies = == Conceptual Designs == . Below are two diagrams which illustrate the proposed method to align the 40m IFO while it is locked. Currently the controls are done using Perl scripting. |
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| ---- This file attachment:40m.pdf contains some results for the 40m ASC sensing matrix. The input for this calculation was taken from 40m web page: http://www.ligo.caltech.edu/~ajw/40m_upgrade.html. The loss per optic was increased from 37.5 ppm to more realistic 100 ppm. == DC Alignment == Below are two diagrams which illustrate the proposed method to align the 40m IFO while it is locked. Currently the controls are done using Perl scripting. In the diagrams the dither signals to the optics are in the YAW axis of the optics, but this is done in a similar manner in the PIT axis. The labels in the colored boxes are the channels (shown in YAW, but valid for PIT as well) to which the obtained error-signals, from the demodulation, are fed back to. |
. In the diagrams the dither signals to the optics are in the YAW axis of the optics, but this is done in a similar manner in the PIT axis. The labels in the colored boxes are the channels (shown in YAW, but valid for PIT as well) to which the obtained error-signals, from the demodulation, are fed back to. |
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== Input signals == . The input signals to ASS are: || '''PD1''' || TRX || || '''PD2''' || TRY || || '''PD3''' || POX33I || || '''PD4''' || POY33I || || '''PD5''' || SP166Q || || '''PD6''' || SPOB66 || || '''PD7''' || AP DC || || '''PD8''' || PO DC || . These are displayed on the ASS MASTER display. = Actual Installations and Operations = == Realtime control model == . Put a diagram of the real time control model == Adjustment of Input/Output Matrices == . Describe how the adjustment have done. == How to run ASS auto-scripts == . {{{ How to do it }}} = ilog and elog entries = * [http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/09/2007&anchor_to_scroll_to=2007:02:10:00:50:51-valera initial commissioning] * [http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/05/2007&anchor_to_scroll_to=2007:02:05:17:53:08-rward Input signals] -- mapping of signals into ASS PD's * [http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/05/2007&anchor_to_scroll_to=2007:02:05:15:03:18-rward compiling the front end code] |
Dither-based Alignment Sensing and Stabilization
Contents
Overview
- The idea is to dither (in pitch and yaw) all of the interferometer optics. We then read out the power (arm powers, PRC power, etc.) and demodulate at the dither frequencies. We can then feedback to control the full interferometer alignment. The concept is the same as what we use to do the initial alignment of the interferometer. It was previously tried by Valera and Bram, but never worked for some reason...
- [attachment:ass.png Conceptual Diagram]
See also the old Alignment Sensing and Control.
Control Topologies
Conceptual Designs
- Below are two diagrams which illustrate the proposed method to align the 40m IFO while it is locked. Currently the controls are done using Perl scripting.
- In the diagrams the dither signals to the optics are in the YAW axis of the optics, but this is done in a similar manner in the PIT axis. The labels in the colored boxes are the channels (shown in YAW, but valid for PIT as well) to which the obtained error-signals, from the demodulation, are fed back to.
attachment:DC_ASC_Inline.png
Figure 1. Diagram of the 40m IFO in-line arm cavity (XARM). The PRM and BS are omitted for clarity.
In-line cavity legend - Figure 1:
IP_POS |
Otherwise known as PZT1, located in front of the PRM. Steers the beam into the IFO. |
IP_ANG |
Otherwise known as PZT2, located after IP_POS and before the PRM. Also, steers the beam into the IFO. |
ITMx |
The ITM of the x-arm, ITMX. |
ETMx |
The ETM of the x-arm, ETMX. |
PDH-err |
The demodulated length control signal, C1:LSC-XARM_IN1. |
TRX |
The transmitted power of the x-arm, C1:LSC-TRX_OUT. |
L.O. ITMx |
Modulation of the ITMx in PIT or YAW using tdssine. |
L.O. ETMx |
Modulation of the ETMx in PIt or YAW using tdssine. |
attachment:DC_ASC_Perp.png
Figure 2. Diagram of the 40m IFO perpendicular arm cavity (YARM).
Perpendicular arm legend - Figure 2:
BS |
Beamsplitter, steers the beam into the perpendicular arm cavity (y-arm). |
ITMy |
The ITM of the y-arm, ITMY. |
ETMy |
The ETM of the y-arm, ETMY. |
PDH-err |
The demodulated length control signal, C1:LSC-YARM_IN1. |
TRY |
The transmitted power of the y-arm, C1:LSC-TRY_OUT. |
L.O. ITMy |
Modulation of the ITMy in PIT or YAW using tdssine. |
L.O. ETMy |
Modulation of the ETMy in PIt or YAW using tdssine. |
Diagram for digital dither alignment scheme of the DRFPMI attachment:40mASC.pdf
Input signals
- The input signals to ASS are:
PD1
TRX
PD2
TRY
PD3
POX33I
PD4
POY33I
PD5
SP166Q
PD6
SPOB66
PD7
AP DC
PD8
PO DC
- These are displayed on the ASS MASTER display.
Actual Installations and Operations
Realtime control model
- Put a diagram of the real time control model
Adjustment of Input/Output Matrices
- Describe how the adjustment have done.
How to run ASS auto-scripts
How to do it
ilog and elog entries
[http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/09/2007&anchor_to_scroll_to=2007:02:10:00:50:51-valera initial commissioning]
[http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/05/2007&anchor_to_scroll_to=2007:02:05:17:53:08-rward Input signals] -- mapping of signals into ASS PD's
[http://www.ldas-sw.ligo.caltech.edu/ilog/pub/ilog.cgi?group=40m&date_to_view=02/05/2007&anchor_to_scroll_to=2007:02:05:15:03:18-rward compiling the front end code]