Differences between revisions 8 and 9
Revision 8 as of 2011-01-27 22:01:44
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Revision 9 as of 2011-01-27 22:02:13
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<<Anchor(ciooFE)>> <<Anchor(c1iooFE)>>

Still under construction

CDS Map

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attachment:yarm.png

Yarm

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[#c1iscexIOFE c1iscex IO/FE]

[#1Y4 1Y4]

attachment:rack.png

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[#c1lscIOFE c1lsc IO/FE]

[#1Y3 1Y3]

attachment:rack.png

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[#1Y2 1Y2]

attachment:rack.png

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[#1Y1 1Y1]

attachment:rack.png

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[#OMC OMC]

attachment:rack.png

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[#1X8 1X8]

attachment:rack.png

Xarm

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attachment:xarm.png

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attachment:rack.png

attachment:rack.png

attachment:rack.png

attachment:rack.png

attachment:rack.png

attachment:rack.png

attachment:rack.png

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[#1X1 1X1]

[#1X2 1X2]

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[#1X3 1X3]

[#1X4 1X4]

[#1X5 1X5]

[#1X6 1X6]

[#1X7 1X7]

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[#1X9 1X9]

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[#c1iooIO c1ioo IO]

[#c1iooFE c1ioo FE]

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[#c1susIOFE c1sus IO/FE]

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[#fb framebuilder]

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[#c1iscexIOFE c1iscex IO/FE]

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Art courtesy of Kiwamu BR BR

1X1

  1. c1ioo IO chassis

    1. Trenton BPX6806 506806, 18 slot PCIe backplane
    2. Timing board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=7093 D070071]

      1. Connects to IO chassis interface
    3. Advanced LIGO IO chassis Interface board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5250 D0902029-V3]

    4. 2 ADCs PMC66-16AI6455A-64-50M [http://www.generalstandards.com/download.php?catid=usermanual&file=pmc16ai64_man_090406.pdf Manual]

      1. ADC 0 is in slot 1, and connects to ADC Adapter Board in slot 1
      2. ADC 1 is in slot 2 and connects to ADC Adapter Board in slot 2
    5. 2 ADL General Standards 16 bit ADC Adapter Board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5190 D0902006]

    6. 1 DAC PMC66-16AO16-16-F0-OF [http://www.generalstandards.com/download.php?catid=usermanual&file=pmc66_16ao16_man_090406.pdf Manual]

      1. DAC 0 is in slot 3 and connects to DAC Adapter Board in slot 3
    7. 1 ADL General Standards 16 bit DAC Adapter Board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=6787 D0902496-v1]

    8. 1 Contec DIO-1616L-PE Isolated Digital IO board [http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1 Manual]

      1. This is in slot 16 and connects to IO chassis Interface
    9. 1 Contec DO-32L-PE Isolated Digital Output Board [http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1 Manual]

      1. BO0 is in slot 8
    10. One Stop Sytems Host interface board OSS-MAX-EXP-ELB-C
      1. This is in the far right slot when looking at the back of the chassis. It connects to the c1ioo FE computer.

1X2

  1. c1ioo FE computer. See CDS Map/c1ioo

    1. GE Fanuc VMIC 5565 with PMC to PCI adapter board [http://defense.ge-ip.com/account/download/1881/1286 Manual]

      1. This connects to the Reflected memory network hub in rack [#1X7 1X7].
    2. One Stop Systems Host interface card OSS-PCIe-HIB2-x4-H [http://www.onestopsystems.com/documents/OSS-PCIe-HIB2-x4-H-T_003.pdf Manual]

      1. This connects to the c1ioo IO chassis.
    3. Runs c1x03 IOP (input output processor). [https://nodus.ligo.caltech.edu:30889/FE/c1x03_slwebview_files/index.html webview]

    4. Runs c1ioo front end model. Input Output Optics [https://nodus.ligo.caltech.edu:30889/FE/c1ioo_slwebview_files/index.html webview]

1X3

1X4

  1. c1sus IO chassis

  2. c1sus FE chassis. See CDS Map/c1sus

    1. GE Fanuc VMIC 5565 with PMC to PCI adapter board [http://defense.ge-ip.com/account/download/1881/1286 Manual]

      1. This connects to the Reflected memory network hub in rack [#1X7 1X7].
    2. Dolphin DXH510 PCI Express Host Adapter
      1. This connects to the Dolphin DXS410 dx 10 Port Switch in rack [#1X4 1X4]
    3. Runs c1x02 IOP (input output processor). [https://nodus.ligo.caltech.edu:30889/FE/c1x02_slwebview_files/index.html webview]

    4. Runs c1sus front end model. Suspensions. [https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html webview]

    5. Runs c1mcs front end model. Mode Cleaner Suspensions. [https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html webview]

    6. Runs c1rfm front end model. Reflected memory. [https://nodus.ligo.caltech.edu:30889/FE/c1rfm_slwebview_files/index.html webview]

    7. Runs c1pem front end model. Physical Environment Monitor. [https://nodus.ligo.caltech.edu:30889/FE/c1pem_slwebview_files/index.html webview]

  3. Dolphin DXS410 dx 10 Port Switch
    1. Connects to c1sus FE computer in [#1X4 1X4] and via fiber to the c1lsc FE computer in rack [#1Y3 1Y3]

1X5

1X6

1X7

1X8

1X9

1Y1

1Y2

1Y3

1Y4

CDS/CDS_Map (last edited 2012-01-03 23:02:38 by localhost)