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← Revision 18 as of 2012-01-03 23:02:38 ⇥
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| Deletions are marked like this. | Additions are marked like this. |
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| || . || . || ||<|16> attachment:yarm.png|| ''''' Yarm ''''' || | || . || . || ||<|16> {{attachment:yarm.png}}|| ''''' Yarm ''''' || |
| Line 8: | Line 8: |
| ||[#c1isceyIOFE c1iscey IO/FE] || [#1Y4 1Y4] || attachment:rack.png|| || | ||[[#c1isceyIOFE|c1iscey IO/FE]] || [[#1Y4|1Y4]] || {{attachment:rack.png}}|| || |
| Line 13: | Line 13: |
| || [#c1lscIOFE c1lsc IO/FE] || [#1Y3 1Y3] || attachment:rack.png|| || || . || [#1Y2 1Y2]|| attachment:rack.png|| || |
|| [[#c1lscIOFE|c1lsc IO/FE]] || [[#1Y3|1Y3]] || {{attachment:rack.png}}|| || || . || [[#1Y2|1Y2]]|| {{attachment:rack.png}}|| || |
| Line 16: | Line 16: |
| || . || [#1Y1 1Y1]||attachment:rack.png || || || . || [#OMC OMC] || || |
|| . || [[#1Y1|1Y1]]||{{attachment:rack.png}} || || || . || [[#OMC|OMC]] || || |
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| || . || . || || || || || || || || || || [#1X8 1X8]|| attachment:rack.png || ''''' Xarm '''''|| || . || . || ||<-30> attachment:xarm.png || || . || . || ||attachment:rack.png ||attachment:rack.png || ||attachment:rack.png ||attachment:rack.png ||attachment:rack.png ||attachment:rack.png || attachment:rack.png || ||attachment:rack.png || || || . || || || || [#1X1 1X1] || [#1X2 1X2] || - - || [#1X3 1X3] || [#1X4 1X4]|| [#1X5 1X5] || [#1X6 1X6]|| [#1X7 1X7]|| - - || [#1X9 1X9]|| - - || || . || || || || [#c1iooIO c1ioo IO] || [#c1iooFE c1ioo FE] || - - || - - || c1sus [#c1susIO IO]/[#c1susFE FE] || - - || [#fb fb] || - - || - - || [#c1iscexIOFE c1iscex IO/FE] || - - || |
|| . || . || || || || || || || || || || [[#1X8|1X8]]|| {{attachment:rack.png}} || ''''' Xarm '''''|| || . || . || ||<-30> {{attachment:xarm.png}} || || . || . || ||{{attachment:rack.png}} ||{{attachment:rack.png}} || ||{{attachment:rack.png}} ||{{attachment:rack.png}} ||{{attachment:rack.png}} ||{{attachment:rack.png}} || {{attachment:rack.png}} || ||{{attachment:rack.png}} || || || . || || || || [[#1X1|1X1]] || [[#1X2|1X2]] || - - || [[#1X3|1X3]] || [[#1X4|1X4]]|| [[#1X5|1X5]] || [[#1X6|1X6]]|| [[#1X7|1X7]]|| - - || [[#1X9|1X9]]|| - - || || . || || || || [[#c1iooIO|c1ioo IO]] || [[#c1iooFE|c1ioo FE]] || - - || - - || c1sus [[#c1susIO|IO]]/[[#c1susFE|FE]] || - - || [[#fb|fb]] || - - || - - || [[#c1iscexIOFE|c1iscex IO/FE]] || - - || |
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| [[BR]] [[BR]] |
<<BR>> <<BR>> |
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| attachment:NetworkTopology.pdf | [[attachment:NetworkTopology.pdf]] |
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| [[BR]] | <<BR>> |
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| A. '''c1ioo''' IO chassis. See [[CDS/CDS Map/c1iooIOchassis]] | A. '''c1ioo''' IO chassis. See [[CDS/CDS_Map/c1iooIOchassis]] |
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| A. '''c1sus''' IO chassis. See [[CDS/CDS Map/c1susIOchassis]] | A. '''c1sus''' IO chassis. See [[CDS/CDS_Map/c1susIOchassis]] |
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| 1. Timing board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=7093 D070071] | 1. Timing board [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=7093|D070071]] |
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| 1. Advanced LIGO IO chassis Interface board [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5250 D0902029-V3] 1. 4 ADCs PMC66-16AI6455A-64-50M [http://www.generalstandards.com/download.php?catid=usermanual&file=pmc16ai64_man_090406.pdf Manual] |
1. Advanced LIGO IO chassis Interface board [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5250|D0902029-V3]] 1. 4 ADCs PMC66-16AI6455A-64-50M [[http://www.generalstandards.com/download.php?catid=usermanual&file=pmc16ai64_man_090406.pdf|Manual]] |
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| 1. 4 ADL General Standards 16 bit ADC Adapter Boards [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5190 D0902006] a. ADC 0 adapter board in slot 3 connects to top anti-aliasing chassis in rack [#1X5 1X5]. a. ADC 1 adapter board in slot 5 connects to bottom Anti-aliasing chassis in rack [#1X5 1X5]. |
1. 4 ADL General Standards 16 bit ADC Adapter Boards [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5190|D0902006]] a. ADC 0 adapter board in slot 3 connects to top anti-aliasing chassis in rack [[#1X5|1X5]]. a. ADC 1 adapter board in slot 5 connects to bottom Anti-aliasing chassis in rack [[#1X5|1X5]]. |
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| a. ADC 3 adapter board in slot 6 connects to anti-aliasing chassis in rack [#1X7 1X7] 1. 3 DACs PMC66-16AO16-16-F0-OF [http://www.generalstandards.com/download.php?catid=usermanual&file=pmc66_16ao16_man_090406.pdf Manual] |
a. ADC 3 adapter board in slot 6 connects to anti-aliasing chassis in rack [[#1X7|1X7]] 1. 3 DACs PMC66-16AO16-16-F0-OF [[http://www.generalstandards.com/download.php?catid=usermanual&file=pmc66_16ao16_man_090406.pdf|Manual]] |
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| 1. 3 ADL General Standards 16 bit DAC Adapter Boards [https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=6787 D0902496-v1] a. DAC 0 adapter board in slot 2 connects to top most DAC to IDC adapter D080303 in rack [#1X5 1X5] a. DAC 1 adapter board in slot 11 connects to middle DAC to IDC adapter D080303 in rack [#1X5 1X5] a. DAC 2 adapter board in slot 10 connects to bottom DAC to IDC adapter D080303 in rack [#1X5 1X5] 1. 1 Contec DIO-1616L-PE Isolated Digital IO board [http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1 Manual] |
1. 3 ADL General Standards 16 bit DAC Adapter Boards [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=6787|D0902496-v1]] a. DAC 0 adapter board in slot 2 connects to top most DAC to IDC adapter D080303 in rack [[#1X5|1X5]] a. DAC 1 adapter board in slot 11 connects to middle DAC to IDC adapter D080303 in rack [[#1X5|1X5]] a. DAC 2 adapter board in slot 10 connects to bottom DAC to IDC adapter D080303 in rack [[#1X5|1X5]] 1. 1 Contec DIO-1616L-PE Isolated Digital IO board [[http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1|Manual]] |
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| 1. 4 Contec DO-32L-PE Isolated Digital Output Board [http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1 Manual] a. BO0 is in slot 9 and connects to top most Binary IO adapter in rack [#1X5 1X5] a. BO1 is in slot 8 and connects to 2nd from the top Binary IO adapter in rack [#1X5 1X5] a. BO2 is in slot 7 and connects to 3rd from the top Binary IO adapter in rack [#1X5 1X5] a. BO3 is in slot 6 and connects to bottom Binary IO adapter in rack [#1X5 1X5] |
1. 4 Contec DO-32L-PE Isolated Digital Output Board [[http://www.contec.com/products/dlrank/dlranklog.cgi?dl=DIO-1616L-PE:LYFY76:1/1|Manual]] a. BO0 is in slot 9 and connects to top most Binary IO adapter in rack [[#1X5|1X5]] a. BO1 is in slot 8 and connects to 2nd from the top Binary IO adapter in rack [[#1X5|1X5]] a. BO2 is in slot 7 and connects to 3rd from the top Binary IO adapter in rack [[#1X5|1X5]] a. BO3 is in slot 6 and connects to bottom Binary IO adapter in rack [[#1X5|1X5]] |
| Line 83: | Line 83: |
| a. This is in the far right slot when looking at the back of the chassis. It connects to the [#c1susFE c1sus FE] computer. | a. This is in the far right slot when looking at the back of the chassis. It connects to the [[#c1susFE|c1sus FE]] computer. |
| Line 86: | Line 86: |
| 1. GE Fanuc VMIC 5565 with PMC to PCI adapter board [http://defense.ge-ip.com/account/download/1881/1286 Manual] a. This connects to the Reflected memory network hub in rack [#1X7 1X7]. |
1. GE Fanuc VMIC 5565 with PMC to PCI adapter board [[http://defense.ge-ip.com/account/download/1881/1286|Manual]] a. This connects to the Reflected memory network hub in rack [[#1X7|1X7]]. |
| Line 89: | Line 89: |
| a. This connects to the Dolphin DXS410 dx 10 Port Switch in rack [#1X4 1X4] | a. This connects to the Dolphin DXS410 dx 10 Port Switch in rack [[#1X4|1X4]] |
| Line 91: | Line 91: |
| a. This connects to the [#c1susIO c1sus IO] chassis. 1. Runs '''c1x02''' IOP (input output processor). [https://nodus.ligo.caltech.edu:30889/FE/c1x02_slwebview_files/index.html webview] 1. Runs '''c1sus''' front end model. Suspensions. [https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html webview] 1. Runs '''c1mcs''' front end model. Mode Cleaner Suspensions. [https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html webview] 1. Runs '''c1rfm''' front end model. Reflected memory. [https://nodus.ligo.caltech.edu:30889/FE/c1rfm_slwebview_files/index.html webview] 1. Runs '''c1pem''' front end model. Physical Environment Monitor. [https://nodus.ligo.caltech.edu:30889/FE/c1pem_slwebview_files/index.html webview] |
a. This connects to the [[#c1susIO|c1sus IO]] chassis. 1. Runs '''c1x02''' IOP (input output processor). [[https://nodus.ligo.caltech.edu:30889/FE/c1x02_slwebview_files/index.html|webview]] 1. Runs '''c1sus''' front end model. Suspensions. [[https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html|webview]] 1. Runs '''c1mcs''' front end model. Mode Cleaner Suspensions. [[https://nodus.ligo.caltech.edu:30889/FE/c1sus_slwebview_files/index.html|webview]] 1. Runs '''c1rfm''' front end model. Reflected memory. [[https://nodus.ligo.caltech.edu:30889/FE/c1rfm_slwebview_files/index.html|webview]] 1. Runs '''c1pem''' front end model. Physical Environment Monitor. [[https://nodus.ligo.caltech.edu:30889/FE/c1pem_slwebview_files/index.html|webview]] |
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| a. Connects to c1sus FE computer in [#1X4 1X4] and via fiber to the c1lsc FE computer in rack [#1Y3 1Y3] | a. Connects to c1sus FE computer in [[#1X4|1X4]] and via fiber to the c1lsc FE computer in rack [[#1Y3|1Y3]] |
Still under construction
CDS Map
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Art courtesy of Kiwamu
Useful Diagrams
1X1
c1ioo IO chassis. See CDS/CDS_Map/c1iooIOchassis
1X2
c1ioo FE computer. Runs c1x03, c1ioo, c1gcv. See CDS/CDS Map/c1ioo
1X3
1X4
c1sus IO chassis. See CDS/CDS_Map/c1susIOchassis
- Trenton BPX6806 506806, 18 slot PCIe backplane
Timing board D070071
- Connects to IO chassis interface
Advanced LIGO IO chassis Interface board D0902029-V3
4 ADCs PMC66-16AI6455A-64-50M Manual
- ADC 0 is in slot 1, and connects to ADC Adapter Board in slot 3
- ADC 1 is in slot 4 and connects to ADC Adapter Board in slot 5
- ADC 2 is in slot 3 and connects to ADC Adapter board in slot 4
- ADC 3 is in slot 5 and connects to ADC Adapter board in slot 6
4 ADL General Standards 16 bit ADC Adapter Boards D0902006
ADC 0 adapter board in slot 3 connects to top anti-aliasing chassis in rack 1X5.
ADC 1 adapter board in slot 5 connects to bottom Anti-aliasing chassis in rack 1X5.
- ADC 2 adapter board in slot 4 connects to DB37 to ADC SCSI Adapter D080302
ADC 3 adapter board in slot 6 connects to anti-aliasing chassis in rack 1X7
3 DACs PMC66-16AO16-16-F0-OF Manual
- DAC 0 is in slot 2 and connects to DAC Adapter Board in slot 2
- DAC 1 is in slot 11 and connects to DAC Adapter Board in slot 11
- DAC 2 is in slot 10 and connects to DAC Adapter Board in slot 10
3 ADL General Standards 16 bit DAC Adapter Boards D0902496-v1
1 Contec DIO-1616L-PE Isolated Digital IO board Manual
- This is in slot 16 and connects to IO chassis Interface
4 Contec DO-32L-PE Isolated Digital Output Board Manual
BO0 is in slot 9 and connects to top most Binary IO adapter in rack 1X5
BO1 is in slot 8 and connects to 2nd from the top Binary IO adapter in rack 1X5
BO2 is in slot 7 and connects to 3rd from the top Binary IO adapter in rack 1X5
BO3 is in slot 6 and connects to bottom Binary IO adapter in rack 1X5
- One Stop Systems expansion link board OSS-MAX-EXP-ELB-C
This is in the far right slot when looking at the back of the chassis. It connects to the c1sus FE computer.
c1sus FE chassis. 6 processors. See CDS/CDS Map/c1susFEcomputer
GE Fanuc VMIC 5565 with PMC to PCI adapter board Manual
This connects to the Reflected memory network hub in rack 1X7.
- Dolphin DXH510 PCI Express Host Adapter
This connects to the Dolphin DXS410 dx 10 Port Switch in rack 1X4
- One Stop Systems host interface board OSS-PCIe-HIB2-x4-H
This connects to the c1sus IO chassis.
Runs c1x02 IOP (input output processor). webview
Runs c1sus front end model. Suspensions. webview
Runs c1mcs front end model. Mode Cleaner Suspensions. webview
Runs c1rfm front end model. Reflected memory. webview
Runs c1pem front end model. Physical Environment Monitor. webview
- Dolphin DXS410 dx 10 Port Switch
1X5
1X6
1X7
1X8
1X9
1Y1
1Y2
1Y3


